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TLP is a test to verify the operational characteristics of the ESD Protection Circuit under ESD stress conditions. While ESD tests such as HBM and CDM can only distinguish Pass or Fail, TLP tests can generate the IV-Curve of the ESD protection circuit inside the IC chip. When an ESD Event occurs, within the internal IC protection Mechanism and the ESD Design window, the operation and margin of the ESD Protection Circuit can be checked. In addition, it is possible to predict the ESD-related reliability level of Chip based on the collected data.

Semiconductor Package Level TLP evaluation

Wafer Level TLP Evaluation

ESD and Electrical Defect Replication TLP Evaluation